Difference between revisions of "MRI lab: FPGA controller documentation"
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| + | ==System== | ||
| + | The design is based on the [http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html Altera DSP Development kit], [http://www.altera.com/products/devices/cyclone3/cy3-index.jsp Cyclone III] edition. The kit includes the [http://www.altera.com/products/devkits/altera/kit-cyc3.html#documentation Cyclone III development board] plus the [http://www.altera.com/literature/manual/rm_data_conversion_hsmc.pdf Data conversion HSMC card]. | ||
| + | |||
| + | See: [[FPGA Design Environment]] | ||
| + | |||
==Control registers== | ==Control registers== | ||
| + | {| border="1" | ||
| + | |- | ||
| + | !Register | ||
| + | !Field | ||
| + | !Bits | ||
| + | !Function | ||
| + | !device | ||
| + | {{ControlRegister|Name=PhaseIncrement|Bits=31:0|Function=Set frequency of generated sinewave|Device=/dev/pio_phaseIncrement}} | ||
| + | {{ControlRegister|Name=Pulse1On|Bits=31:0|Function=Duration of first pulse|Device=/dev/pio_pulse1On}} | ||
| + | {{ControlRegister|Name=Pulse1Off|Bits=31:0|Function=Interval between first and second pulses|Device=/dev/pio_pulse1Off}} | ||
| + | {{ControlRegister|Name=Pulse2On|Bits=31:0|Function=Duration of second pulse|Device=/dev/pio_pulse2On}} | ||
| + | {{ControlRegister|Name=Pulse2Off|Bits=31:0|Function=Minimum interval between end of second pulse and first pulse repeat|Device=/dev/pio_pulse2off}} | ||
| + | |||
| + | |||
| + | {{ControlRegister|Name=adcDelay1|Bits=31:0|Function= | Device=}} | ||
| + | {{ControlRegister|Name=adcCapture1|Bits=31:0|Function=|Device=}} | ||
| + | {{ControlRegister|Name=adcDelay2|Bits=31:0|Function=|Device=}} | ||
| + | {{ControlRegister|Name=adcCapture2|Bits=31:0|Function=|Device=}} | ||
| + | |||
| + | {{ControlRegister|Name=PulseControl||Control bits for pulse generator and digitizer|Device=/dev/pio_pulseControl}} | ||
| + | {{ControlRegister|Bits=13|Field=Digitizer Reset|Function=0 = normal operation; 1 = reset digitizer}} | ||
| + | {{ControlRegister|Bits=12:11|Field=ADC Test mode|Function=00 = adc input (normal operation); 01 = adc test signal (count); 10 = test mode (DAC output); 11 = test mode (constant 0xDEADBEEF)}} | ||
| + | {{ControlRegister|Bits=10:8|Field=ADC clock divisor|Function=not yet implemented}} | ||
| + | {{ControlRegister|Bits=7|Field=WaitDmaComplete|Function=0 = do not wait; 1 = wait for fifo to empty}} | ||
| + | {{ControlRegister|Bits=6|Field=IgnoreDmaReady|Function=0 = normal operation; 1 = ignore}} | ||
| + | {{ControlRegister|Bits=5|Field=RunContinuously|Function=0 = normal operation; 1 = continuous operation}} | ||
| + | {{ControlRegister|Bits=4|Field=Start|Function=Start digitizer on positive edge}} | ||
| + | {{ControlRegister|Bits=3|Field=Reserved|Function=Set to 0}} | ||
| + | {{ControlRegister|Bits=2|Field=DAC B output|Function=0 = carrier; 1 = trigger}} | ||
| + | {{ControlRegister|Bits=1|Field=Continuous Pulse Generation|Function=0 = generate single pulse sequence; 1 = run continuously}} | ||
| + | {{ControlRegister|Bits=0|Field=Start Pulse Generator|Function=Pulse starts on positive edge.}} | ||
| + | |} | ||
==API== | ==API== | ||
Latest revision as of 21:26, 12 April 2011
System
The design is based on the Altera DSP Development kit, Cyclone III edition. The kit includes the Cyclone III development board plus the Data conversion HSMC card.
Control registers
| Register | Field | Bits | Function | device |
|---|---|---|---|---|
| PhaseIncrement | 31:0 | Set frequency of generated sinewave | /dev/pio_phaseIncrement | |
| Pulse1On | 31:0 | Duration of first pulse | /dev/pio_pulse1On | |
| Pulse1Off | 31:0 | Interval between first and second pulses | /dev/pio_pulse1Off | |
| Pulse2On | 31:0 | Duration of second pulse | /dev/pio_pulse2On | |
| Pulse2Off | 31:0 | Minimum interval between end of second pulse and first pulse repeat | /dev/pio_pulse2off
| |
| adcDelay1 | 31:0 | |||
| adcCapture1 | 31:0 | |||
| adcDelay2 | 31:0 | |||
| adcCapture2 | 31:0 | |||
| PulseControl | /dev/pio_pulseControl | |||
| 13 | 0 = normal operation; 1 = reset digitizer | |||
| 12:11 | 00 = adc input (normal operation); 01 = adc test signal (count); 10 = test mode (DAC output); 11 = test mode (constant 0xDEADBEEF) | |||
| 10:8 | not yet implemented | |||
| 7 | 0 = do not wait; 1 = wait for fifo to empty | |||
| 6 | 0 = normal operation; 1 = ignore | |||
| 5 | 0 = normal operation; 1 = continuous operation | |||
| 4 | Start digitizer on positive edge | |||
| 3 | Set to 0 | |||
| 2 | 0 = carrier; 1 = trigger | |||
| 1 | 0 = generate single pulse sequence; 1 = run continuously | |||
| 0 | Pulse starts on positive edge. |
