MRI lab: FPGA controller documentation

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System

The design is based on the Altera DSP Development kit, Cyclone III edition. The kit includes the Cyclone III development board plus the Data conversion HSMC card.

See: FPGA Design Environment

Control registers

Register Field Bits Function device
PhaseIncrement
*
31:0 Set frequency of generated sinewave /dev/pio_phaseIncrement
Pulse1On
*
31:0 Duration of first pulse /dev/pio_pulse1On
Pulse1Off
*
31:0 Interval between first and second pulses /dev/pio_pulse1Off
Pulse2On
*
31:0 Duration of second pulse /dev/pio_pulse2On
Pulse2Off
*
31:0 Minimum interval between end of second pulse and first pulse repeat /dev/pio_pulse2off


adcDelay1
*
31:0
adcCapture1
*
31:0
adcDelay2
*
31:0
adcCapture2
*
31:0
PulseControl
*
/dev/pio_pulseControl
Digitizer Reset
13 0 = normal operation; 1 = reset digitizer
ADC Test mode
12:11 00 = adc input (normal operation); 01 = adc test signal (count); 10 = test mode (DAC output); 11 = test mode (constant 0xDEADBEEF)
ADC clock divisor
10:8 not yet implemented
WaitDmaComplete
7 0 = do not wait; 1 = wait for fifo to empty
IgnoreDmaReady
6 0 = normal operation; 1 = ignore
RunContinuously
5 0 = normal operation; 1 = continuous operation
Start
4 Start digitizer on positive edge
Reserved
3 Set to 0
DAC B output
2 0 = carrier; 1 = trigger
Continuous Pulse Generation
1 0 = generate single pulse sequence; 1 = run continuously
Start Pulse Generator
0 Pulse starts on positive edge.

API