Difference between revisions of "MRI lab: FPGA controller documentation"
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{{ControlRegister|Bits=3|Field=ADC gate enable|Function=0 = normal operation; 1 = disable ADC gate;}} | {{ControlRegister|Bits=3|Field=ADC gate enable|Function=0 = normal operation; 1 = disable ADC gate;}} | ||
{{ControlRegister|Bits=2|Field=DAC B output|Function=0 = carrier; 1 = trigger}} | {{ControlRegister|Bits=2|Field=DAC B output|Function=0 = carrier; 1 = trigger}} | ||
+ | {{ControlRegister|Bits=1|Field=Continuous Pulse Generation|Function=0 = generate single pulse sequence; 1 = run continuously}} | ||
+ | {{ControlRegister|Bits=0|Field=Start Pulse Generator|Function=Pulse starts on positive edge.}} | ||
|} | |} | ||
==API== | ==API== |
Revision as of 15:07, 21 June 2010
Control registers
Register | Field | Bits | Function | device |
---|---|---|---|---|
PhaseIncrement | 31:0 | Set frequency of generated sinewave | /dev/pio_phaseIncrement | |
Pulse1On | 31:0 | Duration of first pulse | /dev/pio_pulse1On | |
Pulse1Off | 31:0 | Interval between first and second pulses | /dev/pio_pulse1Off | |
Pulse2On | 31:0 | Duration of second pulse | /dev/pio_pulse2On | |
Pulse2Off | 31:0 | Minimum interval between end of second pulse and first pulse repeat | /dev/pio_pulse2off | |
PulseControl | /dev/pio_pulseControl | |||
6 | 0 = normal operation; 1 = reset digitizer | |||
5:4 | 00 = adc input (normal operation); 01 = adc test signal (count); 10 = test mode (DAC output); 11 = test mode (constant 0xDEADBEEF) | |||
3 | 0 = normal operation; 1 = disable ADC gate; | |||
2 | 0 = carrier; 1 = trigger | |||
1 | 0 = generate single pulse sequence; 1 = run continuously | |||
0 | Pulse starts on positive edge. |