Difference between revisions of "MRI lab: FPGA controller documentation"
From Course Wiki
| Line 3: | Line 3: | ||
|- | |- | ||
!Register | !Register | ||
| + | !Field | ||
!Bits | !Bits | ||
!Function | !Function | ||
| Line 8: | Line 9: | ||
|- | |- | ||
!PhaseIncrement | !PhaseIncrement | ||
| + | |* | ||
|31:0 | |31:0 | ||
|Frequency of generated sinewave | |Frequency of generated sinewave | ||
| Line 13: | Line 15: | ||
|- | |- | ||
!Pulse1On | !Pulse1On | ||
| + | |* | ||
|31:0 | |31:0 | ||
|Length of first pulse | |Length of first pulse | ||
| Line 18: | Line 21: | ||
|- | |- | ||
!Pulse1Off | !Pulse1Off | ||
| + | |* | ||
|31:0 | |31:0 | ||
|Interval between first and second pulse | |Interval between first and second pulse | ||
| Line 23: | Line 27: | ||
|- | |- | ||
!Pulse2On | !Pulse2On | ||
| + | |* | ||
|31:0 | |31:0 | ||
|Length of second pulse | |Length of second pulse | ||
| Line 28: | Line 33: | ||
|- | |- | ||
!Pulse2On | !Pulse2On | ||
| + | |* | ||
|31:0 | |31:0 | ||
|Interval between second pulse and end of cycle | |Interval between second pulse and end of cycle | ||
| Line 33: | Line 39: | ||
|- | |- | ||
!PulseControl | !PulseControl | ||
| + | | | ||
| | | | ||
| | | | ||
|/dev/pio_pulse2On | |/dev/pio_pulse2On | ||
|- | |- | ||
| + | | | ||
|ADC DMA source | |ADC DMA source | ||
|5:4 | |5:4 | ||
| Line 42: | Line 50: | ||
| | | | ||
|- | |- | ||
| + | | | ||
|ADC gate enable | |ADC gate enable | ||
|3 | |3 | ||
Revision as of 02:05, 18 June 2010
Control registers
| Register | Field | Bits | Function | device |
|---|---|---|---|---|
| PhaseIncrement | * | 31:0 | Frequency of generated sinewave | /dev/pio_phaseIncrement |
| Pulse1On | * | 31:0 | Length of first pulse | /dev/pio_pulse1On |
| Pulse1Off | * | 31:0 | Interval between first and second pulse | /dev/pio_pulse1Off |
| Pulse2On | * | 31:0 | Length of second pulse | /dev/pio_pulse2On |
| Pulse2On | * | 31:0 | Interval between second pulse and end of cycle | /dev/pio_pulse2Off |
| PulseControl | /dev/pio_pulse2On | |||
| ADC DMA source | 5:4 | 00 = adc input (normal operation); 01 = adc test signal (count); 10 = test mode (DAC output); 11 = test mode (constant 0xDEADBEEF) | ||
| ADC gate enable | 3 | 0 = enable; 1 = disable (always valid) |
