MRI lab: FPGA controller documentation
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Revision as of 10:18, 26 June 2010 by Steven Wasserman (Talk | contribs)
System
The design is based on the Altera DSP Development kit, Cyclone III edition. This system consists of the Cyclone III development board plus the Data conversion HSMC card.
Control registers
Register | Field | Bits | Function | device |
---|---|---|---|---|
PhaseIncrement | 31:0 | Set frequency of generated sinewave | /dev/pio_phaseIncrement | |
Pulse1On | 31:0 | Duration of first pulse | /dev/pio_pulse1On | |
Pulse1Off | 31:0 | Interval between first and second pulses | /dev/pio_pulse1Off | |
Pulse2On | 31:0 | Duration of second pulse | /dev/pio_pulse2On | |
Pulse2Off | 31:0 | Minimum interval between end of second pulse and first pulse repeat | /dev/pio_pulse2off | |
PulseControl | /dev/pio_pulseControl | |||
13 | 0 = normal operation; 1 = reset digitizer | |||
12:11 | 00 = adc input (normal operation); 01 = adc test signal (count); 10 = test mode (DAC output); 11 = test mode (constant 0xDEADBEEF) | |||
10:8 | not yet implemented | |||
7 | 0 = do not wait; 1 = wait for fifo to empty | |||
6 | 0 = normal operation; 1 = ignore | |||
5 | 0 = normal operation; 1 = continuous operation | |||
4 | Start digitizer on positive edge | |||
3 | Set to 0 | |||
2 | 0 = carrier; 1 = trigger | |||
1 | 0 = generate single pulse sequence; 1 = run continuously | |||
0 | Pulse starts on positive edge. |